1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a contact hole structure in a semiconductor device.
2. Description of Related Art
Semiconductor integrated circuits formed on a semiconductor substrate, and particularly, a silicon semiconductor substrate, are continuously increasing in integration density and in integration scale, particularly, for example, the integrated circuit typified by a SRAM (static random access memory) has increased its integration scale from 1 megabits to 4 megabits and more. In addition, the SRAM is required to have a high operation speed and also to have a low electric consumption.
Furthermore, large scale integrated circuits including SRAMs and DRAMs (dynamic random access memory) are required not only to form on a single chip as many devices as possible, but also to have a chip size as small as possible in view of the cost per-product and the yield of production. Here, the reduction of the chip size depends upon how each memory cell is reduced. In particular, for reduction of memory cell size in an SRAM having a complicated memory cell structure and requiring a fine patterning, it has become important to consider a method for reducing spacing between a contact hole in the memory cell and another semiconductor device pattern. Here, the semiconductor device pattern includes a source/drain diffusion layer pattern for a transistor, a gate electrode pattern for a transistor, a wiring conductor pattern for a power supply, a device isolation insulator pattern, etc.
Under the circumstances mentioned above, how to apply a self-aligned contact hole has been considered, but there is a case in which the self-aligned contact hole cannot be applied. This is a case of forming a contact hole for interconnecting a gate electrode and a diffused layer. In this case, it was a conventional practice to form a contact hole which extends over the gate electrode pattern and the diffused layer. This contact hole will be called a "common contact hole" in this specification.
Now, this prior art will be explained with reference to FIGS. 1A and 1B. FIG. 1A is a layout pattern diagram illustrating the "common contact hole" which extends over the gate electrode pattern and the diffused layer, and FIG. 1B is a sectional view taken along the line A--A in FIG. 1A.
As shown in FIGS. 1A and 1B, a device isolation insulator film as designated by Reference Numerals 102 and 102A is formed on a p-type silicon substrate 101, and n.sup.+ diffused layers 103 and 103A are formed in a device formation region defined by the device isolation insulator film. In addition, a gate insulator film 104 for a MOS (metal-oxide-semiconductor) field effect transistor is formed to cover a surface of the substrate. Thereafter, the gate insulator film 104 is selectively etched to form a first contact hole 105. Then, a gate electrode as designated by Reference Numerals 106 and 106A is formed. Here, as shown in FIG. 1B, the gate insulator film 104 is removed within the first contact hole 105, so that the n.sup.+ diffused layer 103 is electrically connected to the gate electrode 106 within the first contact 103 is electrically connected to the gate electrode 106 within the first contact hole 105.
Thereafter, a first interlayer insulator film 107 is formed, and then, a first wiring conductor as designated by Reference Numerals 108 and 108A is formed. Furthermore, a second interlayer insulator film 109 is formed to cover the first wiring conductor 108 and 108A.
In order to connect the gate electrode 106 and the n.sup.+ diffused layer 103 to one common wiring conductor, a second contact hole 110 is formed through the first interlayer insulator film 107 and the second interlayer insulator 109. As shown in FIG. 1B, this second contact hole 110 is formed to extend over the gate electrode 106 and the n.sup.+ diffused layer 103, so that the second contact hole 110 becomes a common contact hole which is rectangular in a plan view.
As mentioned above, in the case of interconnecting a conductive member pattern of the semiconductor device such as the above mentioned gate electrode, and another conductive member such as the above mentioned n.sup.+ diffused layer, and also of connecting these two conductive members to one common wiring conductor, the formation of the common contact hole extending over these two conductive members is very effective in increasing the integration density of the semiconductor device.
However, in the prior art as mentioned above, if the design rule of the semiconductor device becomes 0.5 .mu.m or less, the size of the common contact hole is correspondingly made to 0.5 .mu.m or less. In this case, when a fine rectangular contact shape in a mask is transferred to a photoresist film, a completed common contact hole pattern is deformed to a barrel shape having an expanded intermediate part. Namely, as shown in FIG. 1A, the second contact hole 110 formed in the interlayer insulator film has a short side direction size which is enlarged in an intermediate part. As a result, the distance between the second contact hole 110 and another conductor pattern formed above the two conductive members, for example, a periphery 108B of the first wiring conductor 108 shown in FIG. 1A surrounding the contact hole 110, becomes short. This makes difficult the alignment between different patterns in a photolithographic process, and therefore, makes difficult the fine patterning of the semiconductor device element in this region.
The restriction of the fine patterning in the semiconductor device element due to the deformation of the contact hole, is an important problem to be solved for increasing the integration density and the integration size of the semiconductor device, when a circuit pattern is repeated in the semiconductor device as in the SRAM.